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1 of 22 features ? real-time clock (rtc) counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap-year compensation valid up to 2100 ? 96-byte, battery-backed nv ram for data storage ? two time-of-day alarms, programmable on combination of seconds, minutes, hours, and day of the week ? 1hz and 32.768khz clock outputs ? supports motorola spi ? (serial peripheral interface) modes 1 and 3 or standard 3-wire interface ? burst mode for reading/writing successive addresses in clock/ram ? dual-power supply pins for primary and backup power supplies ? optional trickle charge output to backup supply ? 2.0v to 5.5v operation ? optional industrial temperature range: -40c to +85c ? available in space-efficient, 20-pin tssop package ? underwriters laboratory (ul) recognized pin configurations www.maxim-ic.com DS1306 serial alarm real-time clock spi is a trademark of motorola, inc. tssop (4.4mm) v cc2 v bat x1 n.c. x2 n.c. i nt0 int1 1hz gnd v cc1 n.c. 32khz v ccif sdo sdi sclk ce sermode n.c. 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v cc2 dip (300 mils) 15 x1 i nt0 1hz gnd v cc1 sdo sdi sclk ce sermode 1 2 3 4 5 6 7 8 16 14 13 12 11 10 9 v bat x2 int1 32khz v ccif 19-5056; rev 12/09
DS1306 2 of 22 ordering information part temp range pin-package top mark* DS1306 0c to +70c 16 dip (300 mils) DS1306 DS1306+ 0c to +70c 16 dip (300 mils) DS1306 + DS1306n -40c to +85c 16 dip (300 mils) DS1306n DS1306n+ 0c to +70c 16 dip (300 mils) DS1306n + DS1306e 0c to +70c 20 tssop (173 mils) DS1306 DS1306e+ 0c to +70c 20 tssop (173 mils) DS1306 + DS1306en -40c to +85c 20 tssop (173 mils) DS1306n DS1306en+ -40c to +85c 20 tssop (173 mils) DS1306n + DS1306en/t&r -40c to +85c 20 tssop (173 mils) DS1306n DS1306en+t&r -40c to +85c 20 tssop (173 mils) DS1306n + DS1306e/t&r 0c to +70c 20 tssop (173 mils) DS1306 DS1306e+t&r 0c to +70c 20 tssop (173 mils) DS1306 + +denotes a lead(pb)-free/ rohs-compliant package t&r = tape and reel. *an ?n? on the top mark indicates an industrial device. pin description pin tssop dip name function 1 1 v cc2 backup power supply. this is the secondary power supply pin. in systems using the trickle charger, the rechargeab le energy source is connected to this pin. 2 2 v bat battery input for any standard +3v lithium cell or other energy source. if not used, v bat must be connected to ground. diodes must not be placed in series between v bat and the battery, or improper operation will result. ul recognized to ensure agains t reverse charging current when used in conjunction with a lithium battery. see ?conditions of acceptability? at www.maxim-ic.com/techsupport/qa/ntrl.htm . 3 3 x1 5 4 x2 connections for standard 32.768khz quartz crystal. the internal oscillator is designed for operation w ith a crystal having a specified load capacitance of 6pf. for more informa tion on crystal selection and crystal layout considerations, refer to application note 58 , ?crystal considerations with dallas real-time clocks.? the DS1306 can also be driven by an external 32.768khz oscillator. in this c onfiguration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. 7 5 int0 active-low interrupt 0 output. the int0 pin is an active-low output of the DS1306 that can be used as an interrupt input to a processor. the int0 pin can be programmed to be asserted by alarm 0. the int0 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. the int0 pin operates when the DS1306 is powered by v cc1 , v cc2 , or v bat . the int0 pin is an open-drain output and requires an external pullup resistor. 8 6 int1 interrupt 1 output. the int1 pin is an active-high output of the DS1306 that can be used as an interrupt input to a processor. the int1 pin can be programmed to be asserted by alarm 1. when an alarm condition is present, the int1 pin generates a 62.5ms active-high pulse. the int1 pin operates only when the DS1306 is powered by v cc2 or v bat . when active, the int1 pin is internally pulled up to v cc2 or v bat . when inactive, the int1 pin is internally pulled low.
DS1306 3 of 22 pin description (continued) pin tssop dip name function 9 7 1hz 1hz output. the 1hz pin provides a 1hz square wave output. this output is active when the 1 hz bit in the c ontrol register is a logic 1. both int0 and 1hz pins are open-drain outputs. the interrupt, 1hz signal, and the internal clock continue to run regardless of the level of v cc (as long as a power source is present). 10 8 gnd ground 11 9 sermode serial interface mode. the sermode pin offers the flexibility to choose between two serial interface modes. when connected to gnd, standard 3-wire communication is selected. when connected to v cc , spi communication is selected. 12 10 ce chip enable. the chip enable signal must be asserted high during a read or a write for both 3-wire and spi communication. this pin has an internal 55k? pulldown resistor (typical). 14 11 sclk serial clock. sclk is used to synchroni ze data movement on the serial interface for either the spi or 3-wire interface. 15 12 sdi serial data in. when spi communication is selected, the sdi pin is the serial data input for the spi bus. when 3-wire communication is selected, this pin must be tied to the sdo pin (the sdi and sdo pins function as a single i/o pin when tied together). 16 13 sdo serial data out. when spi communication is selected, the sdo pin is the serial data output for the spi bus. when 3-wire communication is selected, this pin must be tied to the sdi pin (the sdi and sdo pins function as a single i/o pin when tied together). v ccif provides the logic-high level. 17 14 v ccif interface logic power-supply input. the v ccif pin allows the DS1306 to drive sdo and 32khz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to 3v logic in mixed supply systems. this pin is physically connected to the source connection of the p-channel transistors in the output buffers of the sdo and 32khz pins. 18 15 32khz 32.768khz output. the 32khz pin provides a 32.768khz output. this signal is always present. v ccif provides the logic-high level. 20 16 v cc1 primary power supply. dc power is provided to the device on this pin. v cc1 is the primary power supply. 4, 6, 13, 19 ? n.c. no connection
DS1306 4 of 22 description the DS1306 serial alarm real-time clock (rtc) provi des a full binary code d decimal (bcd) clock calendar that is accessed by a simple serial interf ace. the clock/calendar provides seconds, minutes, hours, day, date, month, and year info rmation. the end of the month date is automatically adjusted for months with fewer than 31 days, in cluding corrections for leap year. th e clock operates in either the 24- hour or 12-hour format with am/pm indicator. in a ddition, 96 bytes of nv ram are provided for data storage. an interface logic power-supply input pin (v ccif ) allows the DS1306 to drive sdo and 32khz pins to a level that is compatible with the interface logic. this allows an easy interface to 3v logic in mixed supply systems. the DS1306 offers dual-power supplies as we ll as a battery-input pi n. the dual-power supplies support a programmable trickle charge circuit that allows a rechargeable energy source (such as a super cap or rechargeable battery) to be used for a backup supply. the v bat pin allows the device to be backed up by a non-rechargeable battery. the DS1306 is fully operational from 2.0v to 5.5v. two programmable time-of-day alarms are provi ded by the DS1306. each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and day. ?don?t care? states can be inserted into one or more fields if it is desired for them to be ignored for the al arm condition. a 1hz and a 32khz clock output are also available. the DS1306 supports a direct interface to spi serial da ta ports or standard 3-wire interface. an easy-to- use address and data format is implemented in whic h data transfers can occur 1 byte at a time or in multiple-byte burst mode. operation the block diagram in figure 1 show s the main elements of the serial alarm rtc. the following paragraphs describe the function of each pin. figure 1. block diagram 1hz
DS1306 5 of 22 recommended layout for crystal clock accuracy the accuracy of the clock is dependent upon the accur acy of the crystal and the accuracy of the match between the capacitive load of the oscillator circui t and the capacitive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit can result in the clock running fast. refer to application note 58: crystal considerations with dallas real-time clocks for detailed information. table 1. crystal specifications parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6 pf * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal consid erations for dallas real-time clocks for additional specifications. clock, calendar, and alarm the time and calendar information is obtained by r eading the appropriate register bytes. the rtc registers are illustrated in figure 2. the time, cale ndar, and alarm are set or initialized by writing the appropriate register bytes. note that some bits are set to 0. these bits always read 0 regardless of how they are written. also note that registers 12h to 1fh (read ) and registers 92h to 9f h are reserved. these registers always read 0 regardless of how they are written. the contents of the time, calendar, and alarm registers are in the bcd format.. va lues in the day register that corr espond to the day of the week are user-defined, but must be sequent ial (e.g. if 1 equals sunday, 2 eq uals monday and so on). the day register increments at midnight . illogical time and date entrie s result in undefined operation. writing to the clock registers the internal time and date registers continue to increment during write operations. however, the countdown chain is reset when the seconds register is written. writing the time a nd date registers within one second after writing the seconds register ensures consistent data. terminating a write before the last bit is sent aborts the write for that byte. reading from the clock registers buffers are used to copy the time and date register at the beginning of a read. when reading in burst mode, the user copy is static while the internal register s continue to increment. local ground plane (layer 2) crystal x1 x2 gnd
DS1306 6 of 22 figure 2. rtc register s and address map hex address read write bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 range 00h 80h 0 10 sec sec 00?59 01h 81h 0 10 min min 00?59 p 12 a 01?12 + p/a 02h 82h 0 24 10 10-hr hours 00?23 03h 83h 0 0 0 0 0 day 01?07 04h 84h 0 0 10-date date 1?31 05h 85h 0 0 10-month month 01?12 06h 86h 10-year year 00?99 07h 87h m 10-sec alarm 0 sec alarm 0 00?59 08h 88h m 10-min alarm 0 min alarm 0 00?59 p 12 a 01?12 + p/a 09h 89h m 24 10 10-hr hour alarm 0 00?23 0ah 8ah m 0 0 0 0 day alarm 0 01?07 0bh 8bh m 10 sec alarm 1 sec alarm 1 00?59 0ch 8ch m 10 min alarm 1 min alarm 1 00?59 p 12 a 01?12 + p/a 0dh 8dh m 24 10 10-hr hour alarm 1 00?23 0eh 8eh m 0 0 0 0 day alarm 1 01?07 ? 0fh 8fh control register ? 10h 90h status register ? 11h 91h trickle charger register ? 12h?1fh 92h? 9fh reserved ? 20h?7fh a0h? ffh 96-bytes user ram ? note: range for alarm registers does not include mask?m? bits. the DS1306 can be run in either 12-hour or 24-hour mode . bit 6 of the hours regi ster is defined as the 12- or 24-hour mode select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic-high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). the DS1306 contains two time-of-day alarms. time-of- day alarm 0 can be set by writing to registers 87h to 8ah. time-of-day alarm 1 can be set by writing to registers 8bh to 8eh. bit 7 of each of the time-of- day alarm registers are mask bits (table 2). when a ll of the mask bits are logic 0, a time-of-day alarm only occurs once per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time-of-day alarm registers. an alarm is generated every day when bit 7 of the day alarm register is set to a logic 1. an alarm is genera ted every hour when bit 7 of the day and hour alarm
DS1306 7 of 22 registers is set to a logic 1. similarly, an alarm is generated every minute when bit 7 of the day, hour, and minute alarm registers is set to a logic 1. when bit 7 of the day, hour, minute, a nd seconds alarm registers is set to a logic 1, an al arm occurs every second. during each clock update, the rtc compares the alarm 0 and alarm 1 register s with the corresponding clock registers. when a match occurs, the corresponding alar m flag bit in the status register is set to a 1. if the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated. table 2. time-of-day alarm mask bits alarm register mask bits (bit 7) seconds minutes hours days function 1 1 1 1 alarm once per second 0 1 1 1 alarm when seconds match 0 0 1 1 alarm when minutes and seconds match 0 0 0 1 alarm hours, minutes, and seconds match 0 0 0 0 alarm day, hours, minutes and seconds match special purpose registers the DS1306 has three additional register s (control register, status regist er, and trickle charger register) that control the real-time clock, interrupts, and trickle charger. control register (read 0fh, write 8fh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 wp 0 0 0 1hz aie1 aie0 wp (write protect) ? before any write operati on to the clock or ram, this bit must be logic 0. when high, the write protect bit prevents a write operation to any register , including bits 0, 1, and 2 of the control register. upon initial power-u p, the state of the wp bit is undefi ned. therefore, the wp bit should be cleared before attempting to write to the device. wh en wp is set, it must be cleared before any other control register bit can be written. 1hz (1hz output enable) ? this bit controls the 1hz output. w hen this bit is a logic 1, the 1hz output is enabled. when this bit is a l ogic 0, the 1hz output is high-z. aie0 (alarm interrupt enable 0) ? w hen set to a logic 1, this bit permits the interrupt 0 request flag (irqf0) bit in the status register to assert int0 . when the aie0 bit is set to logic 0, the irqf0 bit does not initiate the int0 signal. aie1 (alarm interrupt enable 1) ? w hen set to a logic 1, this bit permits the interrupt 1 request flag (irqf1) bit in the status register to assert int1. when the aie1 bit is set to logic 0, the irqf1 bit does not initiate an interrupt signal, and th e int1 pin is set to a logic 0 state.
DS1306 8 of 22 status register (read 10h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 irqf1 irqf0 irqf0 (interrupt 0 request flag) ? a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 0 registers. if the aie0 bit is also a logic 1, the int0 pin goes low. irqf0 is cleared when the address pointer goes to any of the alarm 0 registers during a read or write. irqf0 is activated when the device is powered by v cc1 , v cc2 , or v bat . irqf1 (interrupt 1 request flag) ? a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 1 registers. if the aie1 b it is also a logic 1, the in t1 pin generates a 62.5ms active-high pulse. irqf1 is cleared when the address pointer goes to any of the alarm 1 registers during a read or write. irqf1 is activated only when the device is powered by v cc2 or v bat . trickle charge register (read 11h, write 91h) this register controls the trickl e charge characteristics of the DS1306. the simplif ied schematic of figure 3 shows the basic components of the trickle charger. the trickle charge select (tcs) bits (bits 4?7) control the selection of the trickle charger. in order to pr event accidental enabling, only a pattern of 1010 enables the trickle charger. all other patterns disable the trickle ch arger. the DS1306 powers up with the trickle charger disabled. the diode select (ds) bits (bits 2?3) select whether one diode or two diodes are connected between v cc1 and v cc2 . the diode select (ds) bits (bits 2?3) select whether one diode or two diodes are connected between v cc1 and v cc2 . the resistor select (rs) bits select the resistor that is connected between v cc1 and v cc2 . the resistor and diodes are selected by the rs and ds bits as shown in table 3. figure 3. programmable trickle charger
DS1306 9 of 22 table 3. trickle charger re sistor and diode select tcs bit 7 tcs bit 6 tcs bit 5 tcs bit 4 ds bit 3 ds bit 2 rs bit 1 rs bit 0 function x x x x x x 0 0 disabled x x x x 0 0 x x disabled x x x x 1 1 x x disabled 1 0 1 0 0 1 0 1 1 diode, 2k ? 1 0 1 0 0 1 1 0 1 diode, 4k ? 1 0 1 0 0 1 1 1 1 diode, 8k ? 1 0 1 0 1 0 0 1 2 diodes, 2k ? 1 0 1 0 1 0 1 0 2 diodes, 4k ? 1 0 1 0 1 0 1 1 2 diodes, 8k ? 0 1 0 1 1 1 0 0 initial power-on state if rs is 00, the trickle charger is disabled independently of tcs. diode and resistor selection is de termined by the user according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculate d as illustrated in the following example. assume that a system power supply of 5v is applied to v cc1 and a super cap is connected to v cc2 . also assume that the trickle charger has b een enabled with one diode and resister r1 between v cc1 and v cc2 . the maximum current i max would, therefore, be calculated as follows: i max = (5.0v - diode drop) / r1 | (5.0v - 0.7v) / 2k ? | 2.2ma as the super cap charges, the voltage drop between v cc1 and v cc2 decreases and, therefore, the charge current decreases. power control power is provided through the v cc1 , v cc2 , and v bat pins. three different pow er supply configurations are illustrated in figure 4. configuration 1 show s the DS1306 being backed up by a non-rechargeable energy source such as a lithium battery. in this conf iguration, the system power supply is connected to v cc1 and v cc2 is grounded. when v cc falls below v bat the device switches into a low-current battery backup mode. upon power-up, the device switches from v bat to v cc when v cc is greater than v bat + 0.2v. the device is write-protected whenever it is switched to v bat . configuration 2 illustrates the DS1306 being backed up by a rechargeable energy source. in this case, the v bat pin is grounded, v cc1 is connected to the primary power supply, and v cc2 is connected to the secondary supply (the rechargeable energy source). the DS1306 operates from the larger of v cc1 or v cc2 . when v cc1 is greater than v cc2 + 0.2v (typical), v cc1 powers the DS1306. when v cc1 is less than v cc2 , v cc2 powers the DS1306. the DS1306 does not write-pro tect itself in this configuration. configuration 3 shows the DS1306 in battery-operate mode, where the device is powered only by a single battery. in this case, the v cc1 and v bat pins are grounded and the batt ery is connected to the v cc2 pin. only these three configurations are allo wed. unused supply pins must be grounded.
DS1306 10 of 22 figure 4. power-supply configurations note: device does not provide automatic write protection. note: device is write-protected if v cc < v cctp . configuration 1: backup supply is nonrechargeable lithium battery configuration 2: backup supply is a rechargeable battery or super capacitor configuration 3: battery operate mode
DS1306 11 of 22 serial interface the DS1306 offers the flexibility to choose betw een two serial interface modes. the DS1306 can communicate with the spi interface or with a standa rd 3-wire interface. the interface method used is determined by the sermode pin. when this pin is connected to v cc , spi communication is selected. when this pin is connected to ground, sta ndard 3-wire communication is selected. serial peripheral interface (spi) the serial peripheral interface (spi) is a synchronous bus for address and data transfer and is used when interfacing with the spi bus on specific motorola microcontrollers such as the 68hc05c4 and the 68hc11a8. the spi mode of seri al communication is selected by tying the sermode pin to v cc . four pins are used for the spi. the f our pins are the sdo (serial data out ), sdi (serial data in), ce (chip enable), and sclk (serial clock). the DS1306 is the slave device in an spi application, with the microcontroller being the master. the sdi and sdo pins are the seri al data input and output pins for the DS1306, respectively. the ce input is used to initiate and terminate a data tran sfer. the sclk pin is us ed to synchronize data movement between the master (microc ontroller) and the slav e (DS1306) devices. the shift clock (sclk), which is generated by the mi crocontroller, is active only during address and data transfer to any device on the spi bus. the in active clock polarity is programmable in some microcontrollers. the DS1306 determines on the clock polarity by sampling sclk when ce becomes active. therefore either sc lk polarity can be accommodated. input da ta (sdi) is latched on the internal strobe edge and output data (sdo) is shifted out on the shift edge (figure 5). there is one clock for each bit transferred. address and da ta bits are transferred in groups of eight, msb first. figure 5. serial clock as a function of microcontroller clock polarity (cpol) ce cpol = 1 sclk data latch (write) shift data out (read) cpol = 0 sclk data latch (write) shift data out (read) note 1: cpha bit polarity (if applicable) may need to be set accordingly. note 2: cpol is a bit that is set in th e microcontroller?s control register. note 3: sdo remains at high-z until 8 bits of data are ready to be shifted out during a read.
DS1306 12 of 22 address and data bytes address and data bytes are shifted msb first into the serial data input (sdi) a nd out of the serial data output (sdo). any transfer requires the address of the byt e to specify a write or read to either a rtc or ram location, followed by one or more bytes of data. data is transferred out of the sdo for a read operation and into the sdi for a wr ite operation (figures 6 and 7). figure 6. spi single-byte write figure 7. spi single-byte read the address byte is always the first byte entered after ce is driven high. the mo st significant bit (a7) of this byte determines if a read or write takes place. if a7 is 0, one or more read cycles occur. if a7 is 1, one or more write cycles occur. data transfers can occur one byte at a time or in multiple-byte burst mode. after ce is driven high an address is written to the DS1306. afte r the address, 1 or more data by tes can be written or read. for a single-byte transfer, one byte is read or written and then ce is driven low. for a multiple-byte transfer, however, multiple bytes can be read or written to the DS1306 after the address has been written. each read or write cycle causes the rtc register or ram address to automatically increment. incrementing continues until the device is disabled. when the rtc is selected, the address wraps to 00h after incrementing to 1fh (during a read) and wraps to 80h after incrementing to 9fh (during a write). when the ram is selected, the address wraps to 20h after incrementing to 7fh (durin g a read) and wraps to a0h after incrementing to ffh (during a write). * sclk can be either polarity. * sclk can be either polarity. sermode = v cc sermode = v cc
DS1306 13 of 22 figure 8. spi multiple-byte burst transfer reading and writing in burst mode burst mode is similar to a single-byte read or wr ite, except that ce is kept high and additional sclk cycles are sent until the end of the burst. the clock registers and the user ram ma y be read or written in burst mode. when accessing the clock registers in bur st mode, the address pointer will wrap around after reaching 1fh (9fh for writes). when accessing the user ram in burst mode, the address pointer wraps around after reaching 7fh (ffh for writes). 3-wire interface the 3-wire interface mode operates si milar to the spi mode. however, in 3-wire mode there is one i/o instead of separate data in and data out signals. th e 3-wire interface consists of the i/o (sdi and sdo pins tied together), ce, and sclk pins. in 3-wire mode, each byte is shifted in lsb first, unlike spi mode, where each byte is shifted in msb first. as is the case with the spi mode, an address byte is written to the device followed by a single data byte or multiple data bytes. figure 9 illustrates a read and write cycle. in 3-wire mode, data is input on the rising edge of sclk and output on the falling edge of sclk.
DS1306 14 of 22 figure 9. 3-wire single byte transfer note: in burst mode, ce is kept high and additional sclk cycles are sent until the end of the burst. * i/o is sdi and sdo tied together. a0 a1 a2 a3 a4 a5 a6 1 ce sclk i/o* d0 d1 d2 d3 d4 d5 d6 d7 single-byte write d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 0 i/o* ce sclk single-byte read sermode = gnd
DS1306 15 of 22 absolute maxi mum ratings voltage range on any pin relative to ground?????????????????..-0.5v to +7.0v storage temperature range????????????????????????.-55 ?c to +125 ?c soldering temperature.????????????.refer to the ipc/jedec standard j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ra ting conditions for extended periods of time can affect reliability. operating range range temp range v cc (v) commercial 0c to +70c 2.0 to 5.5 v cc1 or v cc2 industrial -40c to +85c 2.0 to 5.5 v cc1 or v cc2 recommended dc oper ating conditions (t a = over the operating range, unless otherwise specified.) parameter symbol min typ max units notes supply voltage v cc1 , v cc2 v cc1 , v cc2 2.0 5.5 v 1, 8 logic 1 input v ih 2.0 v cc + 0.3 v v cc = 2.0v +0.3 logic 0 input v il v cc = 5v -0.3 +0.8 v v bat battery voltage v bat 2.0 5.5 v v ccif supply voltage v ccif 2.0 5.5 v 10
DS1306 16 of 22 dc electrical characteristics (t a = over the operating range, unless otherwise specified.) parameter symbol min typ max units notes input leakage i li -100 +500 ? a output leakage i lo -1 +1 ? a i ol = 1.5ma v cc = 2.0 0.4 logic 0 output i ol = 4.0ma v ol v cc = 5v 0.4 v i oh = -0.4ma v ccif = 2.0v 1.6 logic 1 output i oh = -1.0ma v oh v ccif = 5v 2.4 v logic 1 output current (int1 pin) i oh , int1 (v cc2 , v bat ) -0.3v -100 ? a v cc1 = 2.0v 0.425 v cc1 active supply current i cc1a v cc1 = 5v 1.28 ma 2, 7 v cc1 = 2.0v 25.3 v cc1 timekeeping current i cc1t v cc1 = 5v 81 ? a 1, 7 v cc2 = 2.0v 0.4 v cc2 active supply current i cc2a v cc2 = 5v 1.2 ma 2, 8 v cc2 = 2.0v 0.4 v cc2 timekeeping current i cc2t v cc2 = 5v 1 ? a 1, 8 battery timekeeping current i bat v bat = 3v 550 na 9 battery timekeeping current (ind) i bat v bat = 3v 800 na 9 v cc trip point v cctp v bat - 50 v bat + 200 mv r1 2 r2 4 trickle charge resistors r3 8 k ? trickle charger diode voltage drop v td 0.7 v capacitance (t a = +25 ?c) parameter symbol min typ max units notes input capacitance c i 10 pf output capacitance c o 15 pf
DS1306 17 of 22 3-wire ac electrical characteristics (t a = over the operating range, unless otherwise specified. ) (figure 10 and figure 11) parameter symbol min typ max units notes v cc = 2.0v 200 data to clk setup t dc v cc = 5v 50 ns 3, 4 v cc = 2.0v 280 clk to data hold t cdh v cc = 5v 70 ns 3, 4 v cc = 2.0v 800 clk to data delay t cdd v cc = 5v 200 ns 3, 4, 5 v cc = 2.0v 1000 clk low time t cl v cc = 5v 250 ns 4 v cc = 2.0v 1000 clk high time t ch v cc = 5v 250 ns 4 v cc = 2.0v 0.6 clk frequency t clk v cc = 5v dc 2.0 mhz 4 v cc = 2.0v 2000 clk rise and fall t r , t f v cc = 5v 500 ns v cc = 2.0v 4 ce to clk setup t cc v cc = 5v 1 ? s 4 v cc = 2.0v 240 clk to ce hold t cch v cc = 5v 60 ns 4 v cc = 2.0v 4 ce inactive time t cwh v cc = 5v 1 ? s 4 v cc = 2.0v 280 ce to output high-z t cdz v cc = 5v 70 ns 3, 4 v cc = 2.0v 280 sclk to output high-z t ccz v cc = 5v 70 ns 3, 4
DS1306 18 of 22 figure 10. timing diagram: 3-wire read data transfer figure 11. timing diagram: 3-wire write data transfer * i/o is sdi and sdo tied together. * i/o is sdi and sdo tied together. sermode = gnd sermode = gnd
DS1306 19 of 22 spi ac electrical characteristics (t a = over the operating range, unless otherwise specified.) parameter symbol min typ max units notes v cc = 2.0v 200 data to clk setup t dc v cc = 5v 50 ns 3, 4 v cc = 2.0v 280 clk to data hold t cdh v cc = 5v 70 ns 3, 4 v cc = 2.0v 800 clk to data delay t cdd v cc = 5v 200 ns 3, 4, 5 v cc = 2.0v 1000 clk low time t cl v cc = 5v 250 ns 4 v cc = 2.0v 1000 clk high time t ch v cc = 5v 250 ns 4 v cc = 2.0v 0.6 clk frequency t clk v cc = 5v dc 2.0 mhz 4 v cc = 2.0v 2000 clk rise and fall t r , t f v cc = 5v 500 ns v cc = 2.0v 4 ce to clk setup t cc v cc = 5v 1 ? s 4 v cc = 2.0v 240 clk to ce hold t cch v cc = 5v 60 ns 4 v cc = 2.0v 4 ce inactive time t cwh v cc = 5v 1 ? s 4 v cc = 2.0v 280 ce to output high-z t cdz v cc = 5v 70 ns 3, 4
DS1306 20 of 22 figure 12. timing diagram: spi read data transfer figure 13. timing diagram: spi write data transfer * sclk can be either polarity, timing shown for cpol = 1. * sclk can be either polarity, timing shown for cpol = 1. sermode = v cc sermode = v cc
DS1306 21 of 22 notes: 1) i cc1t and i cc2t are specified with ce set to a logic 0. 2) i cc1a and i cc2a are specified with ce = v cc , sclk = 2mhz at v cc = 5v; sclk = 500khz at v cc = 2.0v, v il = 0v, v ih = v cc . 3) measured at v ih = 2.0v or v il = 0.8v and 10ms maximum rise and fall time. 4) measured with 50pf load. 5) measured at v oh = 2.4v or v ol = 0.4v. 6) v cc = v cc1 , when v cc1 > v cc2 + 0.2v (typical); v cc = v cc2 , when v cc2 > v cc1 . 7) v cc2 = 0v. 8) v cc1 = 0v. 9) v cc1 < v bat . 10) v ccif must be less than or e qual to the largest of v cc1 , v cc2 , and v bat . package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type packag e code document no. 16 pdip p16+1 21-0043 20 tssop u20+1 21-0066
DS1306 22 of 22 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered tradema rk of maxim integrated products, inc. revision history revision date description pages changed added table 1. crystal specifications to the clock accuracy section. 5 added ?sermode = v cc ? to figures 6, 7, 12, and 13. 12, 20 added ?sermode = gnd? to figures 9, 10, and 11. 14, 18 12/09 removed the ?crystal capacitance? parameter from the capacitance table. 16

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